| A review of tunnel field-effect transistors for improved ON-state behaviour KRN Karthik, CK Pandey Silicon 15 (1), 1-23, 2023 | 28 | 2023 |
| Design and investigation of a novel gate-all-around vertical tunnel FET with improved DC and analog/RF parameters KRN Karthik, CK Pandey ECS Journal of Solid State Science and Technology 11 (11), 111007, 2022 | 22 | 2022 |
| A review on emerging tunnel FET structures for high-speed and low-power circuit applications CK Pandey, D Das, RNK Kadava, T Ashok, KP Anil, RKG Siva 2023 IEEE Devices for Integrated Circuit (DevIC), 163-167, 2023 | 5 | 2023 |
| GaSb/GaAs Type‐II heterojunction GAA‐TFET with core source for enhanced analog/RF performance and reliability KRN Karthik, CK Pandey International Journal of Numerical Modelling: Electronic Networks, Devices …, 2024 | 4 | 2024 |
| Source Extended GaSb/GaAs Heterojunction GAATFET to Improve ION/IOFF Ratio KRN Karthik, CK Pandey, A Singh, U Nanda 2022 IEEE International Conference of Electron Devices Society Kolkata …, 2022 | 4 | 2022 |
| Tunnel field-effect Transistor (TFET) with gate-all-around epitaxial layer CKP KRN Karthik IN Patent 23/2,453, 2023 | | 2023 |
| DESIGN AND VERIFICATION OF FSM BASED TIMING GENERATOR CIRCUIT USING HDL KRN Karthik, P Kaveri, F Noorbasha International Journal of Advances in Engineering & Technology 6 (3), 1325, 2013 | | 2013 |
| Cadence Design of clock/calendar using 240*8 bit RAM using Verilog HDL KRN Karthik | | |
Dr. Chandan Kumar PandeyAssistant Professor (School of Electronics Engineering), VIT-AP UniversityVerified email at vitap.ac.in
