Malay Ganai
Malay Ganai
Principal Engineer, Synopsys
Verified email at synopsys.com
Title
Cited by
Cited by
Year
Robust Boolean reasoning for equivalence checking and functional property verification
A Kuehlmann, V Paruthi, F Krohm, MK Ganai
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002
3162002
System and method for modeling, abstraction, and analysis of software
F Ivancic, PN Ashar, M Ganai, A Gupta, Z Yang
US Patent 7,346,486, 2008
2092008
Circuit-based Boolean reasoning
A Kuehlmann, MK Ganai, V Paruthi
Proceedings of the 38th Design Automation Conference (IEEE Cat. No …, 2001
1792001
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
MK Ganai, P Ashar, A Gupta, L Zhang, S Malik
Proceedings of the 39th annual Design Automation Conference, 747-750, 2002
1502002
F-Soft: Software Verification Platform
F Ivančić, Z Yang, MK Ganai, A Gupta, I Shlyakhter, P Ashar
International Conference on Computer Aided Verification, 301-306, 2005
1372005
Efficient SAT-based bounded model checking for software verification
F Ivančić, Z Yang, MK Ganai, A Gupta, P Ashar
Theoretical Computer Science 404 (3), 256-274, 2008
1232008
Model checking C programs using F-Soft
F Ivancic, I Shlyakhter, A Gupta, MK Ganai, V Kahlon, C Wang, Z Yang
2005 International Conference on Computer Design, 297-308, 2005
1132005
Accelerating high-level bounded model checking
MK Ganai, A Gupta
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006
982006
Iterative abstraction using SAT-based BMC with proof analysis
A Gupta, M Ganai, Z Yang, P Ashar
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
972003
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
MK Ganai, A Gupta, P Ashar
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
882004
Symbolic predictive analysis for concurrent programs
C Wang, S Kundu, M Ganai, A Gupta
International Symposium on Formal Methods, 256-272, 2009
862009
SAT-based scalable formal verification solutions
M Ganai, A Gupta
Springer Science+ Business Media, 2007
822007
Enhancing simulation with BDDs and ATPG
MK Ganai, A Aziz, A Kuehlmann
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 385-390, 1999
821999
Trace-based symbolic analysis for atomicity violations
C Wang, R Limaye, M Ganai, A Gupta
International Conference on Tools and Algorithms for the Construction and …, 2010
802010
Learning from BDDs in SAT-based bounded model checking
A Gupta, M Ganai, C Wang, Z Yang, P Ashar
Proceedings of the 40th annual Design Automation Conference, 824-829, 2003
652003
Deciding separation logic formulae by SAT and incremental negative cycle elimination
C Wang, F Ivančić, M Ganai, A Gupta
International Conference on Logic for Programming Artificial Intelligence …, 2005
522005
Integrating ICP and LRA solvers for deciding nonlinear real arithmetic problems
S Gao, M Ganai, F Ivančić, A Gupta, S Sankaranarayanan, EM Clarke
Formal Methods in Computer Aided Design, 81-89, 2010
512010
Partial order reduction for scalable testing of SystemC TLM designs
S Kundu, M Ganai, R Gupta
2008 45th ACM/IEEE Design Automation Conference, 936-941, 2008
482008
Iterative abstraction using SAT-based BMC with proof analysis
A Gupta, M Ganai, Z Yang, P Ashar
US Patent 7,742,907, 2010
462010
Efficient modeling of concurrent systems in BMC
MK Ganai, A Gupta
International SPIN Workshop on Model Checking of Software, 114-133, 2008
462008
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