Puneet Sharma
Puneet Sharma
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Title
Cited by
Cited by
Year
Gate-length biasing for runtime-leakage control
P Gupta, AB Kahng, P Sharma, D Sylvester
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
1292006
Selective gate-length biasing for cost-effective runtime leakage control
P Gupta, AB Kahng, P Sharma, D Sylvester
Proceedings of the 41st annual Design Automation Conference, 327-330, 2004
1152004
Exploiting STI stress for performance
AB Kahng, P Sharma, RO Topaloglu
2007 IEEE/ACM International Conference on Computer-Aided Design, 83-90, 2007
862007
Study of floating fill impact on interconnect capacitance
AB Kahng, K Samadi, P Sharma
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-696, 2006
422006
Chip optimization through STI-stress-aware placement perturbations and fill insertion
AB Kahng, P Sharma, RO Topaloglu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
382008
Defocus-aware leakage estimation and control
AB Kahng, S Muddu, P Sharma
IEEE transactions on computer-aided design of integrated circuits and …, 2008
332008
Interconnect modeling for improved system-level design optimization
L Carloni, AB Kahng, S Muddu, A Pinto, K Samadi, P Sharma
2008 Asia and South Pacific Design Automation Conference, 258-264, 2008
322008
Lithography simulation-based full-chip design analyses
P Gupta, AB Kahng, S Nakagawa, S Shah, P Sharma
Design and Process Integration for Microelectronic Manufacturing IV 6156, 61560T, 2006
312006
Layout-aware scan chain synthesis for improved path delay fault coverage
P Gupta, AB Kahng, II Mandoiu, P Sharma
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
272005
A practical transistor-level dual threshold voltage assignment methodology
P Gupta, AB Kahng, P Sharma
Sixth international symposium on quality electronic design (isqed'05), 421-426, 2005
252005
Fill for shallow trench isolation CMP
AB Kahng, P Sharma, A Zelikovsky
2006 IEEE/ACM International Conference on Computer Aided Design, 661-668, 2006
202006
Eyecharts: Constructive benchmarking of gate sizing heuristics
P Gupta, AB Kahng, A Kasibhatla, P Sharma
Design Automation Conference, 597-602, 2010
192010
Accurate predictive interconnect modeling for system-level design
LP Carloni, AB Kahng, SV Muddu, A Pinto, K Samadi, P Sharma
IEEE transactions on very large scale integration (VLSI) systems 18 (4), 679-684, 2009
162009
Lens aberration aware timing-driven placement
AB Kahng, CH Park, P Sharma, Q Wang
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
162006
Impact of gate-length biasing on threshold-voltage selection
AB Kahng, S Muddu, P Sharma
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-754, 2006
142006
Method and system for wafer topography-aware integrated circuit design analysis and optimization
P Gupta, A Kahng, P Sharma, S Muddu
US Patent 8,024,675, 2011
132011
Joining the design and mask flows for better and cheaper masks
P Gupta, AB Kahng, CH Park, P Sharma, DMC Sylvester, J Yang
24th Annual BACUS Symposium on Photomask Technology 5567, 318-329, 2004
132004
Data processing device design tool and methods
MS Abadir, A Gupta, KS Khouri, P Sharma
US Patent 8,127,258, 2012
112012
An uncalibrated lightfield acquisition system
P Sharma, A Parashar, S Banerjee, P Kalra
Image and Vision Computing 22 (14), 1197-1202, 2004
112004
Integrated circuit device with reduced leakage and method therefor
P Sharma, MS Abadir, SP Warrick
US Patent 8,898,614, 2014
82014
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