| Hardwired Networks on Chip in FPGAs to Unify Functional and Configuration Interconnects K Goossens, M Bennebroek, JY Hur, MA Wahlah Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 45-54, 2008 | 57 | 2008 |
| FPGA implementation of parallel histogram computation A Shahbahrami, JY Hur, B Juurlink, S Wong 2nd HiPEAC Workshop on Reconfigurable Computing, 63-72, 2008 | 41 | 2008 |
| METHOD AND APPARATUS FOR PERFORMING ADAPTIVE MEMORY BANK ADDRESSING JY Hur, SW Rhim, BH Lee US Patent 8,817,033, 2015 | 36 | 2015 |
| System-on-chip and address translation method thereof using a translation lookaside buffer and a prefetch buffer SM Hong, SJ Lee, JY Hur, JW Kwon, I Park, JJ Lee, JY Jung US Patent 9,645,934, 2017 | 22 | 2017 |
| Systematic customization of on-chip crossbar interconnects JY Hur, T Stefanov, S Wong, S Vassiliadis Reconfigurable Computing: Architectures, Tools and Applications: Third …, 2007 | 22 | 2007 |
| Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs JY Hur, S Wong, S Vassiliadis Lecture Notes in Computer Science 4419, 49-60, 2007 | 15 | 2007 |
| System on chip for updating partial frame of image and method of operating the same JH Roh, KM Kim, YM Song, JH Lee, JY Hur, SM Hong, BT Lee, KM Chun US Patent App. 14/169,410, 2014 | 14 | 2014 |
| Adaptive Linear Address Map for Bank Interleaving in DRAMs JY Hur, SW Rhim, BH Lee, W Jang IEEE Access 7 (1), 129604-129616, 2019 | 13 | 2019 |
| Customisation of on-chip network interconnects and experiments in field-programmable gate arrays JY Hur, T Stefanov, S Wong, K Goossens IET computers & digital techniques 6 (1), 59-68, 2012 | 13 | 2012 |
| Customizing reconfigurable on-chip crossbar scheduler JY Hur, T Stefanov, S Wong, S Vassiliadis 2007 IEEE International Conf. on Application-specific Systems, Architectures …, 2007 | 11 | 2007 |
| Parallel merge sort on a binary tree on-chip network S Wong, S Vassiliadis, JY Hur Proceedings of the 16th Annual Workshop on Circuits, Systems and Signal …, 2005 | 11 | 2005 |
| Contiguity Representation in Page Table for Memory Management Units JY Hur IEEE Transactions on Very Large Scale Integration Systems 27 (1), 147-158, 2019 | 8 | 2019 |
| Bus System Including ID Converter and Converting Method Thereof BH Lee, SW Rhim, EC Lim, JY Hur US Patent 9,021,169, 2015 | 8 | 2015 |
| Customizing and hardwiring on-chip interconnects in FPGAs JY Hur TU Delft, 2011 | 8 | 2011 |
| A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices T Marconi, JY Hur, K Bertels, G Gaydadjiev 2010 IEEE 8th Symposium on Application Specific Processors (SASP), 87-92, 2010 | 8 | 2010 |
| Block level TLB coalescing for buddy memory allocator JY Hur IEICE TRANSACTIONS on Information and Systems 102 (10), 2043-2046, 2019 | 6 | 2019 |
| Representing contiguity in page table for memory management units JY Hur IEEE Int’l Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC …, 2017 | 6 | 2017 |
| Page Table Compaction for TLB Coalescing JY Hur, J Kong IEEE Access 8 (1), 104814-104829, 2020 | 5 | 2020 |
| Partially reconfigurable point-to-point FPGA interconnects JY Hur, S Wong, S Vassiliadis International Journal of Electronics 95 (7), 725-742, 2008 | 5 | 2008 |
| COHERENT INTERCONNECT FOR MANAGING SNOOP OPERATION AND DATA PROCESSING APPARATUS INCLUDING THE SAME JY Hur, SM Hong US Patent 10,198,357, 2019 | 4 | 2019 |
Stephan WongAssociate Professor, Computer Engineering, TU DelftVerified email at tudelft.nl
