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Cesar Roda Neve, PhD
Cesar Roda Neve, PhD
R&D Program Manager at SOITEC
Verified email at soitec.com - Homepage
Title
Cited by
Cited by
Year
Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer
DC Kerr, JM Gering, TG McKay, MS Carroll, C Roda Neve, JP Raskin
Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008. IEEE …, 2008
1832008
RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates
C Roda Neve, JP Raskin
IEEE Transactions on Electron Devices 59 (4), 924-932, 2012
1142012
RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer
KB Ali, CR Neve, A Gharsallah, JP Raskin
2012 IEEE International SOI Conference (SOI), 1-2, 2012
832012
RF performance of SOI CMOS technology on commercial 200-mm enhanced signal integrity high resistivity SOI substrate
KB Ali, CR Neve, A Gharsallah, JP Raskin
IEEE Transactions on Electron Devices 61 (3), 722-728, 2014
682014
Ultrawide frequency range crosstalk into standard and trap-rich high resistivity silicon substrates
KB Ali, CR Neve, A Gharsallah, JP Raskin
IEEE Transactions on Electron Devices 58 (12), 4258-4264, 2011
442011
RF MEMS passives on high-resistivity silicon substrates
Y Shim, JP Raskin, CR Neve, M Rais-Zadeh
IEEE Microwave and Wireless Components Letters 23 (12), 632-634, 2013
382013
Advanced Si-based substrates for RF passive integration: Comparison between local porous Si layer technology and trap-rich high resistivity Si
P Sarafis, E Hourdakis, AG Nassiopoulou, CR Neve, KB Ali, JP Raskin
Solid-state electronics 87, 27-33, 2013
342013
Impact of Si substrate resistivity on the non-linear behaviour of RF CPW transmission lines
CR Neve, D Lederer, G Pailloncy, DC Kerr, JM Gering, TG McKay, ...
2008 European Microwave Integrated Circuit Conference, 36-39, 2008
332008
Active-lite interposer for 2.5 & 3D integration
G Hellings, M Scholz, M Detalle, D Velenis, MP de ten Broeck, CR Neve, ...
2015 Symposium on VLSI Circuits (VLSI Circuits), T222-T223, 2015
322015
RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications
C Roda Neve, K Ben Alia, C Malaquin, F Allibert, E Desbonnets, ...
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th …, 2013
21*2013
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch
P Schuddinck, FM Bufler, Y Xiang, A Farokhnejad, G Mirabelli, ...
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
162022
Impact of crosstalk into high resistivity silicon substrate on the RF performance of SOI MOSFET
KB Ali, C Roda Neve, A Gharsallah, JP Raskin
J. Telecommun. Informat. Technol. v3 i4, 93-100, 2010
162010
Effect of temperature on advanced Si-based substrates performance for RF passive integration
CR Neve, KB Ali, P Sarafis, E Hourdakis, AG Nassiopoulou, JP Raskin
Microelectronic Engineering 120, 205-209, 2014
152014
Spectral characterisation of monolithic modelocked lasers for mm-wave generation and signal processing
P Acedo, H Lamela, S Garidel, C Roda, JP Vilcot, G Carpintero, IH White, ...
Electronics Letters 42 (16), 928-929, 2006
152006
Optoelectronic up-conversion using compact laterally mode-locked diode lasers
P Acedo, H Lamela, C Roda
IEEE photonics technology letters 18 (17), 1888-1890, 2006
122006
The effect of a SiO2 interface on RF harmonic distortion in CPW lines on silicon or passivated silicon
DC Kerr, JM Gering, T McKay, S Carroll, C Roda Neve, JP Raskin
The 8th Topical Meeting on Silicon Monolithic Integrated Circuits in RF …, 2008
112008
High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer
CR Neve, M Detalle, P Nolmans, Y Li, J De Vos, G Van der Plas, G Beyer, ...
2016 IEEE International 3D Systems Integration Conference (3DIC), 1-4, 2016
92016
Non-linear characteristics of passive elements on trap-rich high-resistivity Si substrates
KB Ali, CR Neve, Y Shim, M Rais-Zadeh, JP Raskin
2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in …, 2014
92014
Photo-induced coplanar waveguide RF switch and optical crosstalk on high-resistivity silicon trap-rich passivated substrate
KB Ali, CR Neve, A Gharsallah, JP Raskin
IEEE transactions on electron devices 60 (10), 3478-3484, 2013
92013
Porous Si as a substrate material for RF passive integration
AG Nassiopoulou, E Hourdakis, P Sarafis, P Ferrari, H Issa, JP Raskin, ...
2013 14th International Conference on Ultimate Integration on Silicon (ULIS …, 2013
92013
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