| A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router J Pu, WL Goh, VP Nambiar, MM Wong, AT Do IEEE Transactions on Circuits and Systems I: Regular Papers 68 (12), 5081-5094, 2021 | 18 | 2021 |
| 0.5 V 4.8 pJ/SOP 0.93\mu\mathrm {W} $ Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron VP Nambiar, J Pu, YK Lee, A Mani, T Luo, L Yang, EK Koh, MM Wong, ... 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2020 | 12 | 2020 |
| A low-cost high-throughput digital design of biorealistic spiking neuron J Pu, WL Goh, VP Nambiar, YS Chong, AT Do IEEE Transactions on Circuits and Systems II: Express Briefs 68 (4), 1398-1402, 2020 | 12 | 2020 |
| Block-based spiking neural network hardware with deme genetic algorithm J Pu, VP Nambiar, AT Do, WL Goh 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 12 | 2019 |
| A low power and low area router with congestion-aware routing algorithm for spiking neural network hardware implementations J Pu, WL Goh, VP Nambiar, AT Do IEEE Transactions on Circuits and Systems II: Express Briefs 68 (1), 471-475, 2020 | 6 | 2020 |
| Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency L Yang, H Zhang, T Luo, C Qu, MTL Aung, Y Cui, J Zhou, MM Wong, J Pu, ... Neurocomputing 474, 128-140, 2022 | 5 | 2022 |
| Power and area efficient router with automated clock gating for neuromorphic computing J Pu, VP Nambiar, A Mani, WL Goh, AT Do 2019 32nd IEEE International System-on-Chip Conference (SOCC), 27-32, 2019 | 5 | 2019 |
| Scalable block-based spiking neural network hardware with a multiplierless neuron model VP Nambiar, EK Koh, J Pu, A Mani, WM Ming, L Fei, WL Goh, AT Do 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 4 | 2020 |
| Neural network processor system and methods of operating and forming thereof V Paramasivam, AT Do, EK Koh, J Pu, F Li, A Mani US Patent App. 17/638,748, 2022 | 2 | 2022 |
| Energy efficient 0.5 V 4.8 pJ/SOP 0.93 μW leakage/core neuromorphic processor design VP Nambiar, J Pu, YK Lee, A Mani, EK Koh, MM Wong, F Li, WL Goh, ... IEEE Transactions on Circuits and Systems II: Express Briefs 68 (9), 3148-3152, 2021 | 2 | 2021 |
| Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers YK Lee, VP Nambiar, J Pu, WL Goh, AT Do 2019 32nd IEEE International System-on-Chip Conference (SOCC), 242-247, 2019 | 2 | 2019 |
| A 110nW Always-on Keyword Spotting Chip using Spiking CNN in 40nm CMOS C Shen, J Pu, Y Chong, Z Zhang, W Goh, B Zhao, AT Do, Y Gao 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | | 2023 |
| Corrigendum to “Coreset:: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency”[Neurocomputing (2022) 128–140] L Yang, H Zhang, T Luo, C Qu, MT Linn Aung, Y Cui, J Zhou, MM Wong, ... | | 2022 |
| Energy efficient neuromorphic computing circuit and architecture design J Pu Nanyang Technological University, 2022 | | 2022 |
