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Majid Rezazadeh
Title
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Cited by
Year
Design and Implementation of Multistage Interconnection Networks for SoC Networks
M Moazez, F Safaei, M Rezazadeh
arXiv preprint arXiv:1212.0310, 2012
42012
Multi-level execution trace based lock contention analysis
M Rezazadeh, N Ezzati-Jivan, E Galea, MR Dagenais
2020 IEEE International Symposium on Software Reliability Engineering …, 2020
22020
Performance evaluation of complex multi-thread applications through execution path analysis
M Rezazadeh, N Ezzati-Jivan, SV Azhari, MR Dagenais
Performance Evaluation 155, 102289, 2022
12022
Comparative Performance Study of Multi-stage Interconnection Networks Using Carbon Nanotube Switches
M Rezazadeh, F Safaei, MH Moaiyeri
Embedded and Ubiquitous Computing (EUC), 2011 IFIP 9th International …, 2011
12011
Performance Analysis of Complex Multi-Thread Applications Through Critical Path Analysis
M Rezazadeh
Ecole Polytechnique, Montreal (Canada), 2019
2019
Flattening: An efficient approach to improving the performance of conventional MINs
M Rezazadeh, F Safaei, M Moazez
Microelectronics Journal 46 (10), 875-892, 2015
2015
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Articles 1–6