| Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops U Khalid, A Mastrandrea, M Olivieri Microelectronics Reliability 55 (12), 2614-2626, 2015 | 34 | 2015 |
| A voltage-based leakage current calculation scheme and its application to nanoscale MOSFET and FinFET standard-cell designs Z Abbas, A Mastrandrea, M Olivieri IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (12 …, 2014 | 33 | 2014 |
| The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes A Cheikh, G Cerutti, A Mastrandrea, F Menichelli, M Olivieri Applications in Electronics Pervading Industry, Environment and Society …, 2019 | 29 | 2019 |
| Klessydra-T: Designing vector coprocessors for multithreaded edge-computing cores A Cheikh, S Sordillo, A Mastrandrea, F Menichelli, G Scotti, M Olivieri IEEE Micro 41 (2), 64-71, 2021 | 28 | 2021 |
| Logic drivers: A propagation delay modeling paradigm for statistical simulation of standard cell designs M Olivieri, A Mastrandrea IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (6 …, 2013 | 21 | 2013 |
| Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores M Olivieri, A Cheikh, G Cerutti, A Mastrandrea, F Menichelli 2017 New Generation of CAS (NGCAS), 45-48, 2017 | 20 | 2017 |
| Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment M Barbirotta, A Mastrandrea, F Menichelli, F Vigli, L Blasi, A Cheikh, ... 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2020 | 18 | 2020 |
| Novel approaches to quantify failure probability due to process variations in nano-scale CMOS logic U Khalid, A Mastrandrea, M Olivieri 2014 29th International Conference on Microelectronics Proceedings-MIEL 2014 …, 2014 | 16 | 2014 |
| Introducing approximate memory support in linux kernel G Stazi, F Menichelli, A Mastrandrea, M Olivieri 2017 13th Conference on Ph. D. Research in Microelectronics and Electronics …, 2017 | 15 | 2017 |
| Design and evaluation of buffered triple modular redundancy in interleaved-multi-threading processors M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, M Olivieri IEEE Access 10, 126074-126088, 2022 | 14 | 2022 |
| Evaluation of dynamic triple modular redundancy in an interleaved-multi-threading risc-v core M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, M Ottavi, M Olivieri Journal of Low Power Electronics and Applications 13 (1), 2, 2022 | 13 | 2022 |
| A Fault Tolerant soft-core obtained from an Interleaved-Multi-Threading RISC-V microprocessor design M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, F Vigli, M Olivieri 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2021 | 13 | 2021 |
| Impact of approximate memory data allocation on a h. 264 software video encoder G Stazi, L Adani, A Mastrandrea, M Olivieri, F Menichelli International Conference on High Performance Computing, 545-553, 2018 | 13 | 2018 |
| A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled watch-dog timer L Blasi, F Vigli, A Cheikh, A Mastrandrea, F Menichelli, M Olivieri Applications in Electronics Pervading Industry, Environment and Society …, 2020 | 12 | 2020 |
| A delay model allowing nano-CMOS standard cells statistical simulation at the logic level A Mastrandrea, F Menichelli, M Olivieri 2011 7th Conference on Ph. D. Research in Microelectronics and Electronics …, 2011 | 12 | 2011 |
| Efficient mathematical accelerator design coupled with an interleaved multi-threading RISC-V microprocessor A Cheikh, S Sordillo, A Mastrandrea, F Menichelli, M Olivieri Applications in Electronics Pervading Industry, Environment and Society …, 2020 | 10 | 2020 |
| A pulp-based parallel power controller for future exascale systems A Bartolini, D Rossi, A Mastrandrea, C Conficoni, S Benatti, A Tilli, ... 2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019 | 9 | 2019 |
| Customizable vector acceleration in extreme-edge computing: a RISC-V software/hardware architecture study on VGG-16 implementation S Sordillo, A Cheikh, A Mastrandrea, F Menichelli, M Olivieri Electronics 10 (4), 518, 2021 | 8 | 2021 |
| Analysis of a fault tolerant edge-computing microarchitecture exploiting vector acceleration M Barbirotta, A Cheikh, A Mastrandrea, F Menichelli, M Olivieri 2022 17th Conference on Ph. D Research in Microelectronics and Electronics …, 2022 | 7 | 2022 |
| Efficient mathematic accelerator design coupled with an IMT RISC-V microprocessor A Cheikh, S Sordillo, A Mastrandrea, F Menichelli, M Olivieri, S Saponara, ... Applepies 2019. Lecture Notes in Electrical Engineering 627 (2020), 505-511, 2020 | 7 | 2020 |
Usman KhalidSapienza University of RomeVerified email at uniroma1.it
