Aditya Rajagopal
Aditya Rajagopal
Senior Compiler Engineer, Qualcomm; PhD Imperial College London
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Multi-Precision Policy Enforced Training (MuPPET): A precision-switching strategy for quantised fixed-point training of CNNs
A Rajagopal, DA Vink, SI Venieris, CS Bouganis
Published at ICML 2020, 2020
Caffe Barista: Brewing Caffe with FPGAs in the Training Loop
DA Vink, A Rajagopal, SI Venieris, CS Bouganis
Published as a short paper at FPL 2020, 2020
perf4sight: A toolflow to model CNN training performance on Edge GPUs
A Rajagopal, CS Bouganis
Proceedings of the IEEE/CVF International Conference on Computer Vision, 963-971, 2021
Now that I can see, I can improve: Enabling data-driven finetuning of CNNs on the edge
A Rajagopal, CS Bouganis
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern …, 2020
GSA to HDL: Towards principled generation of dynamically scheduled circuits
A Rajagopal, DA Vink, J Cheng, Y Herklotz
arXiv preprint arXiv:2308.11048, 2023
Low-Cost On-device Partial Domain Adaptation (LoCO-PDA): Enabling efficient CNN retraining on edge devices
A Rajagopal, CS Bouganis
arXiv preprint arXiv:2203.00772, 2022
Enabling on-device domain adaptation of convolutional neural networks
A Rajagopal
Imperial College London, 2022
intelligent Digital Systems Lab
A Montgomerie, D Vink, A Rajagopal
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