| A High-Performance Inverted-C Tunnel Junction FET With Source–Channel Overlap Pockets Ashita, SA Loan, M Rafat Transactions on Electron Devices 65 (2), 763-768, 2018 | 78* | 2018 |
| Ambipolar leakage suppression in electron–hole bilayer TFET: Investigation and analysis Ashita, AG Alharbi, SA Loan, M Rafat Journal of Computational Electronics 17 (3), 977-985, 2018 | 23 | 2018 |
| [PDF] ieee.org Insights Into the Impact of Pocket and Source Elevation in Vertical Gate Elevated Source Tunnel FET Structures Ashita, SA Loan, M Rafat Transactions on Electron Devices 66 (1), 752-758, 2019 | 22* | 2019 |
| Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET Ashita, HI Alkhammash, SA Loan, M Rafat International Journal of Numerical Modelling: Electronic Networks, Devices …, 2021 | 4 | 2021 |
| A novel finbox EHBTFET for low power applications Ashita, SA Loan, M Rafat 2017 International conference on Microelectronic Devices, Circuits and …, 2017 | 3* | 2017 |
| p-Heterogate Ge EHBTFET with asymmetric dielectric underlap pockets A Ashita, SA Loan, M Rafat 2019 IEEE 14th Nanotechnology Materials and Devices Conference (NMDC), 1-4, 2019 | 1 | 2019 |
| Investigation of leakage in FinEHBTFET with stack-gate underlaps Ashita, SA Loan, M Rafat, SA Abbasi 2017 International Conference on Multimedia, Signal Processing and …, 2017 | 1 | 2017 |
| A FinBOX Based Ge FinEHBTFET: Design and Investigation Ashita, HI Alkhammash, SA Loan, M Rafat Silicon, 1-10, 2021 | | 2021 |
| A Line TFET design employing Tri-line-gate architecture and U-shaped pockets for minimizing drain field effects Ashita, SA Loan, M Rafat 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2019 | | 2019 |
Sajad A LoanProfessor of Electronics Engineering, Jamia Millia Islamia New DelhiVerified email at jmi.ac.in
