P. Balasubramanian
Cited by
Cited by
A fault tolerance improved majority voter for TMR system architectures
P Balasubramanian, K Prasad
WSEAS Transactions on Circuits and Systems 15, Article #14, 108-122, 2016
High speed gate level synchronous full adder designs
P Balasubramanian, NE Mastorakis
WSEAS Transactions on Circuits and Systems 8 (2), 290-300, 2009
RB_DSOP: A rule based disjoint sum of products synthesis method
P Balasubramanian, R Arisaka, HR Arabnia
12th International Conference on Computer Design, 39-43, 2012
Low power digital design using modified GDI method
P Balasubramanian, J John
IEEE International Conference on Design and Test of Integrated Systems in …, 2006
A delay efficient robust self-timed full adder
P Balasubramanian, DA Edwards
IEEE 3rd International Design and Test Workshop, 129-134, 2008
Hardware Optimized and Error Reduced Approximate Adder
P Balasubramanian, DL Maskell
Electronics 8 (11), Article #1212, 1-15, 2019
A robust asynchronous early output full adder
P Balasubramanian
WSEAS Transactions on Circuits and Systems 10 (7), 221-230, 2011
A latency optimized biased implementation style weak-indication self-timed full adder
P Balasubramanian
Facta Universitatis, Series: Electronics and Energetics 28 (4), 657-671, 2015
A distributed minority and majority voting based redundancy scheme
P Balasubramanian, DL Maskell
Microelectronics Reliability 55 (9-10), 1373-1378, 2015
QDI decomposed DIMS method featuring homogeneous/heterogeneous data encoding
P Balasubramanian, NE Mastorakis
International Conference on Computers, Digital Communications and Computing …, 2011
Self-timed realization of combinational logic
P Balasubramanian, DA Edwards
19th International Workshop on Logic and Synthesis (Co-sponsored by ACM …, 2010
Efficient realization of strongly indicating function blocks
P Balasubramanian, DA Edwards
IEEE Computer Society Annual Symposium on VLSI, 429-432, 2008
A new design technique for weakly indicating function blocks
P Balasubramanian, DA Edwards
11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008
Self-timed logic and the design of self-timed adders
P Balasubramanian
The University of Manchester, 2010
Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions
P Balasubramanian, N Mastorakis
Electronics 7 (12), Article #369, 1-12, 2018
Self-timed section-carry based carry lookahead adders and the concept of alias logic
P Balasubramanian, DA Edwards, WB Toms
Journal of Circuits, Systems, and Computers 22 (4), 1350028-1 - 1350028-24, 2013
A set theory based factoring technique and its use for low power logic design
P Balasubramanian, R Arisaka
International Journal of Electrical, Computer and Systems Engineering 1 (3 …, 2007
Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders
P Balasubramanian, S Yamashita
SpringerPlus 5 (440 (1)), 1-26, 2016
A set theory based method to derive network reliability expressions of complex system topologies
P Balasubramanian, NE Mastorakis
Applied Computing Conference, 108-114, 2010
Robust asynchronous implementation of Boolean functions on the basis of duality
P Balasubramanian, K Prasad, NE Mastorakis
14th WSEAS International Conference on Circuits, 37-43, 2010
The system can't perform the operation now. Try again later.
Articles 1–20