‪Sin-Wei Chiu‬ - ‪Google Scholar‬

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Co-authors

Keshab K. ParhiUniversity of Minnesota, Erwin A. Kelen Chair in Electrical EngineeringVerified email at umn.edu
Yingjie LaoTufts UniversityVerified email at tufts.edu

Sin-Wei Chiu

Sin-Wei Chiu

University of Minnesota

Verified email at umn.edu - Homepage

VLSI VLSI Signal Processing Digital Signal Processing Homomorphic Encryption


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PaReNTT: Low-latency parallel residue number system and NTT-based long polynomial modular multiplication for homomorphic encryption W Tan, SW Chiu, A Wang, Y Lao, KK Parhi IEEE Transactions on Information Forensics and Security, 2023	5	2023
Long Polynomial Modular Multiplication Using Low-Complexity Number Theoretic Transform [Lecture Notes] SW Chiu, KK Parhi IEEE Signal Processing Magazine 41 (1), 92-102, 2024	1*	2024
Low-Latency Preprocessing Architecture for Residue Number System via Flexible Barrett Reduction for Homomorphic Encryption SW Chiu, KK Parhi IEEE Transactions on Circuits and Systems II: Express Briefs, 2023		2023

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