Follow
Rasit Onur TOPALOGLU
Rasit Onur TOPALOGLU
Adeia
Verified email at marist.edu
Title
Cited by
Cited by
Year
Exploiting STI stress for performance
AB Kahng, P Sharma, RO Topaloglu
2007 IEEE/ACM International Conference on Computer-Aided Design, 83-90, 2007
952007
Work balancing scheduler for processor cores and methods thereof
RO Topaloglu
US Patent 8,219,994, 2012
622012
Quantum generative models for small molecule drug discovery
J Li, RO Topaloglu, S Ghosh
IEEE transactions on quantum engineering 2, 1-8, 2021
582021
Quantum puf for security and trust in quantum computing
K Phalak, A Ash-Saki, M Alam, RO Topaloglu, S Ghosh
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 11 (2 …, 2021
482021
Self-aligned double patterning decomposition for overlay minimization and hot spot detection
H Zhang, Y Du, MDF Wong, R Topaloglu
Proceedings of the 48th Design Automation Conference, 71-76, 2011
452011
Chip optimization through STI-stress-aware placement perturbations and fill insertion
AB Kahng, P Sharma, RO Topaloglu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
432008
Block-level 3D IC design with through-silicon-via planning
DH Kim, RO Topaloglu, SK Lim
17th Asia and South Pacific Design Automation Conference, 335-340, 2012
412012
ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite
RO Topaloglu
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-4, 2016
402016
New current–mode special function continuous-time active filters employing only OTAs and OPAMPs
ES Erdogan, R Topaloglu, H Kuntman, O Cicekoglu*
International Journal of Electronics 91 (6), 345-359, 2004
362004
More than moore technologies for next generation computer design
RO Topaloglu
Springer, 2015
312015
A DOE set for normalization-based extraction of fill impact on capacitances
AB Kahng, RO Topaloglu
8th International Symposium on Quality Electronic Design (ISQED'07), 467-474, 2007
312007
Vertical silicon-on-metal superconducting quantum interference device
S Rosenblatt, JB Hertzberg, RO Topaloglu, M Brink
US Patent 10,615,223, 2020
302020
Logic synthesis meets machine learning: Trading exactness for generalization
S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ...
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
292021
Is overlay error more important than interconnect variations in double patterning?
K Jeong, AB Kahng, RO Topaloglu
Proceedings of the 11th international workshop on System level interconnect …, 2009
282009
Assessing chip-level impact of double patterning lithography
K Jeong, AB Kahng, RO Topaloglu
2010 11th International Symposium on Quality Electronic Design (ISQED), 122-130, 2010
262010
Short paper: A quantum circuit obfuscation methodology for security and privacy
A Suresh, AA Saki, M Alam, R Onur Topaloglu, S Ghosh
Proceedings of the 10th International Workshop on Hardware and Architectural …, 2021
242021
Characterization and decomposition of self-aligned quadruple patterning friendly layout
H Zhang, Y Du, MDF Wong, RO Topaloglu
Optical Microlithography XXV 8326, 146-156, 2012
242012
A survey and tutorial on security and resilience of quantum computing
AA Saki, M Alam, K Phalak, A Suresh, RO Topaloglu, S Ghosh
2021 IEEE European Test Symposium (ETS), 1-10, 2021
232021
ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite
RO Topaloglu
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 367-368, 2014
232014
Effective decomposition algorithm for self-aligned double patterning lithography
H Zhang, Y Du, MDF Wong, R Topaloglu, W Conley
Optical Microlithography XXIV 7973, 176-186, 2011
232011
The system can't perform the operation now. Try again later.
Articles 1–20