| The gem5 simulator N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ... ACM SIGARCH computer architecture news 39 (2), 1-7, 2011 | 5930 | 2011 |
| The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 252 | 2020 |
| Optimization and mathematical modeling in computer architecture T Nowatzki, MC Ferris, K Sankaralingam, C Estan, N Vaish, DA Wood Morgan & Claypool, 2014 | 42 | 2014 |
| Experiences in co-designing a packet classification algorithm and a flexible hardware platform N Vaish, T Kooburat, L De Carli, K Sankaralingam, C Estan Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for …, 2011 | 11 | 2011 |
| Simulating vector execution BM Beckmann, N Vaish, SK Reinhardt US Patent 9,342,334, 2016 | 9 | 2016 |
| Optimization Models for Three On-Chip Network Problems N Vaish, MC Ferris, DA Wood ACM Transactions on Architecture and Code Optimization (TACO) 13 (3), 26, 2016 | 8 | 2016 |
| MultiProcessor Systems on Field Programmable Gate Arrays R Sahni, N Vaish, K Paul, M Balakrishnan B. Tech final report, Department of Computer Science and Engineering, Indian …, 2007 | 2 | 2007 |
| Characterizing a Memory Allocator at Warehouse Scale Z Zhou, V Gogte, N Vaish, C Kennelly, P Xia, S Kanev, T Moseley, ... | | 2024 |
| A New Implementation for std::sort M Gelmi, D Kutenin, D Mankowitz, A Michi, M Selvi, N Vaish, MJ Hwang Seventh LLVM Performance Workshop, 2023 | | 2023 |
| Optimization-based Models for Pruning the Design-space for Processors N Vaish The University of Wisconsin-Madison, 2017 | | 2017 |
| On Lookups in Content-based Routers A Anand, N Vaish, A Akella 8th USENIX Symposium on Networked Systems Design and Implementation (Poster), 2011 | | 2011 |
| Packet Classification on PLUG Architecture T Kooburat, N Vaish | | 2010 |
David A. WoodUniversity of Wisconsin, MadisonVerified email at cs.wisc.edu
