| In-situ grafting of Au and Cu nanoparticles over graphitic carbon nitride sheets and unveiling its superior supercapacitive performance as a hybrid composite electrode material S Yesmin, M Devi, I Hussain, R Dasgupta, SS Dhar Journal of Energy Storage 44, 103308, 2021 | 19 | 2021 |
| Performance comparison of 1-bit conventional and hybrid full adder circuits I Hussain, S Chaudhury Advances in Communication, Devices and Networking: Proceedings of ICCDN 2017 …, 2018 | 17 | 2018 |
| Design and Analysis of High Performance Multiplier Circuit I Hussain, CK Pandey, S Chaudhury 3rd IEEE international conference on Devices for Integrated Circuit (DevIC …, 2019 | 16 | 2019 |
| Design and performance analysis of a 3-2 compressor by using improved architecture I Hussain, M Kumar Journal of Active and Passive Electronic Devices 12 (3-4), 173-181, 2017 | 15 | 2017 |
| Advances in Communication, Devices and Networking Proceedings of ICCDN 2018 R Bera, SK Sarkar, S Chakraborty Proceedings of ICCDN, 1, 2017 | 13 | 2017 |
| A Fast and Reduced Complexity Wallace Multiplier. I Hussain, M Kumar Journal of Active & Passive Electronic Devices 12, 2017 | 13 | 2017 |
| A review on the effects of technology on CMOS and CPL logic style on performance, speed and power dissipation I Hussain, A Singh, S Chaudhury 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 332-336, 2018 | 12 | 2018 |
| Performance comparison of Wallace multiplier architectures I Hussain, RK Sah, M Kumar International Journal of Innovative Research in Science, Engineering and …, 2015 | 10 | 2015 |
| Performance analysis of a 6T SRAM cell in 180nm CMOS technology RK Sah, I Hussain, M Kumar IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) 5 (2), 20-22, 2015 | 8 | 2015 |
| Performance comparison for different configurations of SRAM cells RK Sah, I Hussain, M Kumar International Journal of Innovative Research in Science, Engineering and …, 2015 | 8 | 2015 |
| CNFET Based Low Power Full Adder Circuit for VLSI Applications I Hussain, S Chaudhury Nanoscience & Nanotechnology-Asia 10 (3), 286 - 291, 2020 | 7 | 2020 |
| Fast and high-performing 1-bit full adder circuit based on input switching activity patterns and gate diffusion input technique I Hussain, S Chaudhury Circuits, Systems, and Signal Processing 40 (4), 1762-1787, 2021 | 6 | 2021 |
| A comparative study on the effects of technology nodes and logic styles for low power high speed VLSI applications I Hussain, S Chaudhury International Journal of Nanoparticles 12 (1-2), 122-135, 2020 | 5 | 2020 |
| Exploration of Cu/g-C3N4 Nanocomposites as a Cost-Effective High-Performance Asymmetric Supercapacitor Electrode Material S Yesmin, I Hussain, M Devi, R Dasgupta, SS Dhar IEEE Transactions on Nanotechnology 21, 474-480, 2022 | 4 | 2022 |
| A New 4-2 Compressor for VLSI Circuits and Systems I Hussain, S Chaudhury International Conference on Frontiers in Smart System Technologies (FSST …, 2019 | 3 | 2019 |
| A Multi-Vt approach for Silicon Nanotube FET with Halo Implantation for improved DIBL A Singh, I Hussain, S Chaudhury, CK Sarkar IEEE Electron Device Kolkata Conference (EDKCON 2018)At: Kolkata, 2018 | 3 | 2018 |
| Design and Analysis of a Conventional Wallace Multiplier in 180nm CMOS Technology I Hussain, M Kumar IOSR Journal of VLSI and Signal Processing 5 (1), 60-65, 2015 | 3 | 2015 |
| Two-dimensional tungsten oxide nanoflakes grafted over g-C3N4 as excellent electrode materials for hybrid supercapacitors S Yesmin, I Hussain, R Dasgupta, SS Dhar Journal of Energy Storage 74, 109383, 2023 | 2 | 2023 |
| Sah,“Performance Comparison of Wallace Multiplier Architectures,” I Hussain, RK Sah International Journal of Innovative Research in Science, Engineering and …, 2015 | 2 | 2015 |
| Performance Analysis Comparison of a Conventional Wallace Multiplier and a Reduced Complexity Wallace multiplier I Hussain, RK Sah, M Kumar IOSR Journal of VLSI and Signal Processing 5 (2), 23-27, 2015 | 2 | 2015 |
Saurabh ChaudhuryProfessor, NIT SilcharVerified email at nits.ac.in
