| Optimal power-area polar decoder design based on iterative decomposition technique HS Kalluru, Z Abbas 2019 IEEE 16th India Council International Conference (INDICON), 1-4, 2019 | 3 | 2019 |
| Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence P Saha, S Ahmed, HS Kalluru, Z Abbas 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 1 | 2021 |
| Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations HS Kalluru, P Saha, A Zahra, Z Abbas 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 1 | 2021 |
| Transistor sizing based pvt-aware low power optimization using swarm intelligence P Saha, HS Kalluru, Z Abbas 2021 34th International Conference on VLSI Design and 2021 20th …, 2021 | 1 | 2021 |
| PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits HS Kalluru, P Saha, A Zahra, Z Abbas 2021 22nd International Symposium on Quality Electronic Design (ISQED), 1-6, 2021 | | 2021 |
| 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID)| 978-1-6654-4087-5/21/$31.00© 2021 IEEE| DOI: 10.1109 … Z Abbas, I Afanasyev, A Agrawal, S Agrawal, V Agrawal, I Alouani, ... | | |
