| Programming programmable logic devices using hidden switches W Feng, WA Oswald, ML Roy, E Ting US Patent 6,496,969, 2002 | 64 | 2002 |
| Designing efficient input interconnect blocks for LUT clusters using counting and entropy W Feng, S Kaptanoglu ACM Transactions on Reconfigurable Technology and Systems (TRETS) 1 (1), 1-28, 2008 | 63 | 2008 |
| A 65nm flash-based FPGA fabric optimized for low cost and power J Greene, S Kaptanoglu, W Feng, V Hecht, J Landry, F Li, A Krouglyanskiy, ... Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011 | 44 | 2011 |
| K-way partitioning based packing for FPGA logic blocks without input bandwidth constraint W Feng 2012 International Conference on Field-Programmable Technology, 8-15, 2012 | 40 | 2012 |
| Improving FPGA performance with a S44 LUT structure W Feng, J Greene, A Mishchenko Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 37 | 2018 |
| Rent's rule based FPGA packing for routability optimization W Feng, J Greene, K Vorwerk, V Pevzner, A Kundu Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014 | 23 | 2014 |
| Technology mapping into general programmable cells A Mishchenko, R Brayton, W Feng, J Greene Proceedings of the 2015 ACM/SIGDA International Symposium on Field …, 2015 | 18 | 2015 |
| Field programmable gate array architecture having Clos network-based input interconnect W Feng, J Greene, S Kaptanoglu US Patent 7,924,052, 2011 | 15 | 2011 |
| Novel control pattern generators for interconnect testing with boundary scan W Feng, FJ Meyer, F Lombardi Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance …, 1999 | 10 | 1999 |
| Logic module including versatile adder for FPGA W Feng, J Greene US Patent 7,772,879, 2010 | 7 | 2010 |
| Reconfiguration of one-time programmable FPGAs with faulty logic resources W Feng, X Chen, FJ Meyer, F Lombardi Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance …, 1999 | 7 | 1999 |
| FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation W Feng, S Kaptanoglu US Patent 7,408,383, 2008 | 6 | 2008 |
| Testing a nanocrossbar for multiple fault detection W Feng, F Lombardi, HAF Almurib, TN Kumar IEEE transactions on nanotechnology 12 (4), 477-485, 2013 | 5 | 2013 |
| Adaptive algorithms for maximal diagnosis of wiring interconnects WY Feng, FJ Meyer, F Lombardi IEEE Transactions on Computers 52 (10), 1259-1270, 2003 | 5 | 2003 |
| Fault detection in a tristate system environment W Feng, F Karimi, F Lombardi IEEE Micro 21 (5), 77-85, 2001 | 5 | 2001 |
| Reconfiguring one-time programmable FPGAs XT Chen, W Feng, J Zhao, FJ Meyer, F Lombardi IEEE Micro 19 (6), 53-63, 1999 | 5 | 1999 |
| Clustered field programmable gate array architecture S Kaptanoglu, W Feng US Patent 7,924,053, 2011 | 4 | 2011 |
| Post-placement interconnect entropy: how many configuration bits does a programmable logic device need? W Feng, JW Greene Proceedings of the 2006 international workshop on System-level interconnect …, 2006 | 4 | 2006 |
| A BIST TPG approach for interconnect testing with the IEEE 1149.1 STD W Feng, WK Huang, FJ Meyer, F Lombardi Proceedings Eighth Asian Test Symposium (ATS'99), 95-100, 1999 | 4 | 1999 |
| Two-step algorithms for maximal diagnosis of wiring interconnects W Feng, FJ Meyer, F Lombardi Digest of Papers. Twenty-Ninth Annual International Symposium on Fault …, 1999 | 4 | 1999 |
Jonathan W GreeneVisiting Scholar, Univ Calif Berkeley; Owner, Cambios Computing LLC.Verified email at cambioscomputing.com
