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Javier D. Bruguera
Javier D. Bruguera
ARM, Cambridge, UK
Verified email at arm.com
Title
Cited by
Cited by
Year
High-speed function approximation using a minimax quadratic interpolator
JA Pineiro, SF Oberman, JM Muller, JD Bruguera
IEEE Transactions on Computers 54 (3), 304-318, 2005
1802005
Leading-one prediction with concurrent position correction
JD Bruguera, T Lang
IEEE Transactions on Computers 48 (10), 1083-1097, 1999
1641999
High performance rotation architectures based on the radix-4 CORDIC algorithm
E Antelo, J Villalba, JD Bruguera, EL Zapata
IEEE Transactions on Computers 46 (8), 855-870, 1997
1641997
High-speed double-precision computation of reciprocal, division, square root, and inverse square root
JA Pineiro, JD Bruguera
Computers, IEEE Transactions on 51 (12), 1377-1388, 2002
1422002
Algorithm and architecture for logarithm, exponential, and powering computation
JA Pineiro, MD Ercegovac, JD Bruguera
IEEE Transactions on Computers 53 (9), 1085-1096, 2004
1222004
Floating-point multiply-add-fused with reduced latency
T Lang, JD Bruguera
IEEE Transactions on Computers 53 (8), 988-1003, 2004
1212004
Floating-point multiply-add-fused with reduced latency
T Lang, JD Bruguera
IEEE Transactions on Computers 53 (8), 988-1003, 2004
1212004
Faithful powering computation using table look-up and a fused accumulation tree
JA Piñeiro, JD Bruguera, JM Muller
Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on, 40-47, 2001
1172001
Floating—Point Fused Multiply–Add with Reduced Latency
JD Bruguera, T Lang
2002 IEEE International Conference on Computer Design (ICCD’02), 145, 2002
113*2002
High-throughput architecture for H. 264/AVC CABAC compression system
RR Osorio, JD Bruguera
IEEE Transactions on Circuits and Systems for Video Technology 16 (11), 1376 …, 2006
1102006
Floating-point fused multiply-add: reduced latency for floating-point addition
JD Bruguera, T Lang
Computer Arithmetic, 2005. ARITH-17 2005. 17th IEEE Symposium on, 42-51, 2005
882005
High-performance VLSI architecture for the Viterbi algorithm
M Bóo, F Arguello, JD Bruguera, R Doallo, EL Zapata
Communications, IEEE Transactions on 45 (2), 168-176, 1997
871997
Arithmetic coding architecture for H. 264/AVC CABAC compression system
RR Osorio, JD Bruguera
Euromicro Symposium on Digital System Design, 2004. DSD 2004., 62-69, 2004
812004
A GIS-embedded system to support land consolidation plans in Galicia
J Touriño, J Parapar, R Doallo, M Boullón, FF Rivera, JD Bruguera, ...
International Journal of Geographical Information Science 17 (4), 377-396, 2003
722003
Cordic based parallel/pipelined architecture for the Hough transform
JD Bruguera, N Guil, T Lang, J Villalba, EL Zapata
Journal of VLSI signal processing systems for signal, image and video …, 1996
521996
CORDIC architectures with parallel compensation of the scale factor
J Villalba, JA Hidalgo, EL Zapata, E Antelo, JD Bruguera
Proceedings The International Conference on Application Specific Array …, 1995
521995
CORDIC architectures with parallel compensation of the scale factor
J Villalba, JA Hidalgo, EL Zapata, E Antelo, JD Bruguera
Proceedings The International Conference on Application Specific Array …, 1995
521995
Unified mixed radix 2-4 redundant CORDIC processor
E Antelo, JD Bruguera, EL Zapata
IEEE transactions on Computers 45 (9), 1068-1073, 1996
501996
Implementation of the FFT butterfly with redundant arithmetic
JD Bruguera, T Lang
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1996
461996
A new architecture for fast arithmetic coding in H. 264 advanced video coder
RR Osorio, JD Bruguera
8th Euromicro Conference on Digital System Design (DSD'05), 298-305, 2005
382005
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