Thomas Shiple
Thomas Shiple
MIT, UC Berkeley, Synopsys
Verified email at alum.mit.edu
Title
Cited by
Cited by
Year
Constructive analysis of cyclic circuits
TR Shiple, G Berry, H Touati
Proceedings ED&TC European Design and Test Conference, 328-333, 1996
1971996
Smart simulation using collaborative formal and simulation engines
PH Ho, T Shiple, K Harer, J Kukula, R Damiano, V Bertacco, J Taylor, ...
IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000
1652000
Heuristic minimization of BDDs using don't cares
TR Shiple, R Hojati, AL Sangiovanni-Vincentelli, RK Brayton
31st Design Automation Conference, 225-231, 1994
1311994
HSIS: A BDD-based environment for formal verification
A Aziz, F Balarin, ST Cheng, R Hojati, T Kam, SC Krishnan, RK Ranjan, ...
Proceedings of the 31st annual Design Automation Conference, 454-459, 1994
991994
Approximation and decomposition of binary decision diagrams
K Ravi, KL McMillan, TR Shiple, F Somenzi
Proceedings of the 35th annual Design Automation Conference, 445-450, 1998
881998
Formal analysis of synchronous circuits
TR Shiple
University of California, Berkeley, 1996
741996
A comparison of Presburger engines for EFSM reachability
TR Shiple, JH Kukula, RK Ranjan
International Conference on Computer Aided Verification, 280-292, 1998
691998
Building circuits from relations
JH Kukula, TR Shiple
International Conference on Computer Aided Verification, 113-123, 2000
592000
Formula-dependent equivalence for compositional CTL model checking
A Aziz, TR Shiple, V Singhal, AL Sangiovanni-Vincentelli
International Conference on Computer Aided Verification, 324-337, 1994
501994
Vis
RK Brayton, GD Hachtel, A Sangiovanni-Vincentelli, F Somenzi, A Aziz, ...
International Conference on Formal Methods in Computer-Aided Design, 248-256, 1996
481996
Analysis of combinational cycles in sequential circuits
TR Shiple, V Singhal, RK Brayton, AL Sangiovnni-Vincentelli
1996 IEEE International Symposium on Circuits and Systems (ISCAS) 4, 592-595, 1996
351996
Constructive Boolean circuits and the exactness of timed ternary simulation
M Mendler, TR Shiple, G Berry
Formal Methods in System Design 40 (3), 283-329, 2012
332012
Automatic compositional minimization in CTL model checking
M Chiodo, TR Shiple, AL Sangiovanni-Vincentelli, RK Brayton
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided …, 1992
251992
VIS User’s Manual
T Villa, G Swamy, T Shiple, A Aziz, R Brayton, S Edwards, G Hachtel, ...
Electronics Research Laboratory, University of Colorado at Boulder, 1996
241996
A unified approach to language containment and fair CTL model checking
R Hojati, TR Shiple, RK Brayton, RP Kurshan
30th ACM/IEEE Design Automation Conference, 475-481, 1993
241993
Simplifying circuits for formal verification using parametric representation
IH Moon, HH Kwak, J Kukula, T Shiple, C Pixley
International Conference on Formal Methods in Computer-Aided Design, 52-69, 2002
202002
Formula-dependent equivalence for compositional CTL model checking
A Aziz, T Shiple, V Singhal, R Brayton, A Sangiovanni-Vincentelli
Formal Methods in System Design 21 (2), 193-224, 2002
192002
Method and system for automata-based approach to state reachability of interacting extended finite state machines
JH Kukula, TR Shiple
US Patent 6,059,837, 2000
192000
Automatic reduction in CTL compositional model checking
TR Shiple, M Chiodo, AL Sangiovanni-Vincentelli, RK Brayton
International Conference on Computer Aided Verification, 234-247, 1992
161992
Combinational equivalence checking through function transformation
HH Kwak, IH Moon, JH Kukula, TR Shiple
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
122002
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