| Quantifying error in dynamic power estimation of CMOS circuits P Gupta, AB Kahng, S Muddu Analog Integrated Circuits and Signal Processing 42, 253-264, 2005 | 34 | 2005 |
| Interconnect modeling for improved system-level design optimization L Carloni, AB Kahng, S Muddu, A Pinto, K Samadi, P Sharma 2008 Asia and South Pacific Design Automation Conference, 258-264, 2008 | 33 | 2008 |
| Defocus-aware leakage estimation and control AB Kahng, S Muddu, P Sharma Proceedings of the 2005 international symposium on Low power electronics and …, 2005 | 33 | 2005 |
| Auxiliary pattern-based optical proximity correction for better printability, timing, and leakage control AB Kahng, S Muddu, CH Park Journal of Micro/Nanolithography, MEMS and MOEMS 7 (1), 013002-013002-13, 2008 | 19 | 2008 |
| Accurate predictive interconnect modeling for system-level design LP Carloni, AB Kahng, SV Muddu, A Pinto, K Samadi, P Sharma IEEE transactions on very large scale integration (VLSI) systems 18 (4), 679-684, 2009 | 17 | 2009 |
| Method and system for wafer topography-aware integrated circuit design analysis and optimization P Gupta, A Kahng, P Sharma, S Muddu US Patent 8,024,675, 2011 | 16 | 2011 |
| Impact of gate-length biasing on threshold-voltage selection AB Kahng, S Muddu, P Sharma 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-754, 2006 | 14 | 2006 |
| Modeling edge placement error distribution in standard cell library P Gupta, AB Kahng, SV Muddu, S Nakagawa Design and Process Integration for Microelectronic Manufacturing IV 6156 …, 2006 | 13 | 2006 |
| Layout pattern correction for integrated circuits R Abou Ghaida, A Mohyeldin, P Pathak, S Muddu, V Dai, L Capodieci US Patent 8,898,606, 2014 | 12 | 2014 |
| Resist heating dependence on subfield scheduling in 50-kV electron beam maskmaking SV Babin, AB Kahng, I Mandoiu, SV Muddu Photomask and Next-Generation Lithography Mask Technology X 5130, 718-726, 2003 | 12 | 2003 |
| A novel metric for interconnect architecture performance P Dasgupta, AB Kahng, S Muddu 2003 Design, Automation and Test in Europe Conference and Exhibition, 448-453, 2003 | 12 | 2003 |
| Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns Y Zou, S Maddu, LT Wang, V Dai, L Capodieci, P Xie US Patent 8,555,215, 2013 | 11 | 2013 |
| Subfield scheduling for throughput maximization in electron-beam photomask fabrication SV Babin, AB Kahng, II Mandoiu, S Muddu Emerging Lithographic Technologies VII 5037, 934-942, 2003 | 9 | 2003 |
| Pattern-based via redundancy insertion S Muddu, S Jiang US Patent 9,189,589, 2015 | 7 | 2015 |
| Detailed placement for leakage reduction using systematic through-pitch variation AB Kahng, S Muddu, P Sharma Proceedings of the 2007 international symposium on Low power electronics and …, 2007 | 6 | 2007 |
| Modeling OPC complexity for design for manufacturability P Gupta, AB Kahng, S Muddu, S Nakagawa, CH Park 25th Annual BACUS Symposium on Photomask Technology 5992, 612-622, 2005 | 6 | 2005 |
| Methods for analyzing design rules S Muddu, AA Kagalwalla, L Capodieci US Patent 8,589,844, 2013 | 5 | 2013 |
| Improving critical dimension accuracy and throughput by subfield scheduling in electron beam mask writing S Babin, AB Kahng, II Măndoiu, S Muddu Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2005 | 5 | 2005 |
| Method and apparatus for applying post graphic data system stream enhancements S Muddu, S Madhavan, S Malik US Patent 8,745,553, 2014 | 3 | 2014 |
| Predictive modeling of lithography-induced linewidth variation AB Kahng, SV Muddu Photomask and Next-Generation Lithography Mask Technology XV 7028, 180-193, 2008 | 3 | 2008 |
