| Hardware Software Co-Simulation of Canny Edge Detection Algorithm KAA Fuad, SM Rizvi International Journal of Computer Applications (IJCA) 122 (19), 7-12, 2015 | 16 | 2015 |
| A Low-complexity Complex-valued Activation Function for Fast and Accurate Spectral Domain Convolutional Neural Network SM Rizvi, AAH Ab Rahman, M Khalil-Hani, SO Ayat Indonesian Journal of Electrical Engineering and Informatics (IJEEI) 9 (1 …, 2021 | 4 | 2021 |
| Computation and memory optimized spectral domain convolutional neural network for throughput and energy-efficient inference SM Rizvi, AAHA Rahman, UU Sheikh, KAA Fuad, HMF Shehzad Applied Intelligence 53 (4), 4499 - 4523, 2023 | 2 | 2023 |
| A Methodology to Remove Unwanted Delays in Outputs and Pre and Post-Synthesis Simulation Mismatches in Implicit State Machines SM Rizvi, JJ Cupal Electronic Design Processes (EDP) Workshop, S5.3 (Day Two, Session Five), 2004 | 1 | 2004 |
| A Compact Spectral Model for Convolutional Neural Network SSA Ayat, S.O., Rizvi, S.M., Abdellatef, H., Ab Rahman, A.AH., Manan Lecture Notes in Networks and Systems 559, 100-120, 2023 | | 2023 |
| A Compact Spectral Model for Convolutional Neural Network SO Ayat, SM Rizvi, H Abdellatef, AAH Ab Rahman, SSA Manan Proceedings of the Future Technologies Conference, 2022 | | 2022 |
| A Compact Spectral Model for Convolutional Neural Network SO Ayat, SM Rizvi, H Abdellatef, AAH Ab Rahman, SSA Manan Proceedings of the Future Technologies Conference (FTC) 2022, Volume 1, 100-120, 2022 | | 2022 |
| A Pseudo Randomly Triggered Integer Cycle Control (PRT-ICC) for AC Loads to Reduce THD, EMI and RFI MR Amin, SM Rizvi, JJ Cupal Journal of Research and Reviews: Journal of Embedded System & Applications …, 2015 | | 2015 |
| Varying Sample-Width to Realize Area-Efficient FPGA Realization of Sobel-Fieldman Edge Detector KAA Fuad, SM Rizvi AIUB Journal of Science and Engineering (AJSE) 14 (1), 123-128, 2015 | | 2015 |
| Hardware/Software Co-Simulation of Gradient-based Edge Detectors: A Comparative Study KAA Fuad, SM Rizvi Journal of Image Processing & Pattern Recognition Progress (JoIPPRP) 2 (3 …, 2015 | | 2015 |
| Tools and Techniques for Safe Synthesis of FSMDs Represented in Behavioral Level Implicit Style Verilog HDL or VHDL SM Rizvi, JJ Cupal, TI Chowdhury, K Mahmood FPGA Designer Forum (at Southern Programmable Logic (SPL) Conference), 15-20, 2007 | | 2007 |
| A Methodology for Retaining Pre-Synthesis Behavior of FSMs modeled in Implicit Style Verilog HDL after Synthesis and Implementation SM Rizvi, JJ Cupal, TI Chowdhury, K Mahmood Jahangirnagar University Journal of Electronics and Computer Science (JUJECS …, 2006 | | 2006 |
| Guidelines for Safe Synthesis of While Loops In Implicit Style Verilog HDL SM Rizvi, JJ Cupal International Conference on Electrical and Computer Engineering (ICECE), 67-71, 2004 | | 2004 |
Kazi Ahmed Asif FuadGraduate Assistant, Oregon State University; Assistant Professor, AIUBVerified email at oregonstate.edu
