Vigyan Singhal
Vigyan Singhal
Oski Technology
Verified email at oskitech.com - Homepage
Title
Cited by
Cited by
Year
Model-checking continuous-time Markov chains
A Aziz, K Sanwal, V Singhal, R Brayton
ACM Transactions on Computational Logic (TOCL) 1 (1), 162-170, 2000
5122000
Verifying continuous time Markov chains
A Aziz, K Sanwal, V Singhal, R Brayton
International Conference on Computer Aided Verification, 269-276, 1996
4061996
It usually works: The temporal logic of stochastic systems
A Aziz, V Singhal, F Balarin, RK Brayton, AL Sangiovanni-Vincentelli
International Conference on Computer Aided Verification, 155-165, 1995
2721995
Tight integration of combinational verification methods
JR Burch, V Singhal
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1998
1221998
BDD based procedures for a theory of equality with uninterpreted functions
A Goel, K Sajid, H Zhou, A Aziz, V Singhal
International Conference on Computer Aided Verification, 244-255, 1998
1201998
HSIS: A BDD-based environment for formal verification
A Aziz, F Balarin, ST Cheng, R Hojati, T Kam, SC Krishnan, RK Ranjan, ...
Proceedings of the 31st annual Design Automation Conference, 454-459, 1994
991994
Formula-dependent equivalence for compositional CTL model checking
A Aziz, TR Shiple, V Singhal, AL Sangiovanni-Vincentelli
International Conference on Computer Aided Verification, 324-337, 1994
501994
BDD decomposition for efficient logic synthesis
C Yang, V Singhal, M Ciesielski
Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999
491999
Minimizing interacting finite state machines: A compositional approach to language containment
A Aziz, V Singhal, R Brayton, GM Swamy
Proceedings 1994 IEEE International Conference on Computer Design: VLSI in …, 1994
481994
Robust latch mapping for combinational equivalence checking
JR Burch, V Singhal
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1998
471998
Analysis of locking behavior in three real database systems
V Singhal, AJ Smith
The VLDB Journal 6 (1), 40-52, 1997
461997
Method for verifying properties of a circuit model
V Singhal, JE Higgins
US Patent 7,020,856, 2006
452006
The validity of retiming sequential circuits
V Singhal
32nd Design Automation Conference, 316-321, 1995
451995
The case for retiming with explicit reset circuitry
V Singhal, S Malik, RK Brayton
Proceedings of International Conference on Computer Aided Design, 618-625, 1996
441996
System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit model
CWN Ip, L Loh, V Singhal, H Wong-Toi, S Myint
US Patent 7,159,198, 2007
432007
Equivalences for fair kripke structures
A Aziz, V Singhal, F Balarin, RK Brayton, AL Sangiovanni-Vincentelli
International Colloquium on Automata, Languages, and Programming, 364-375, 1994
371994
Method and system for combinational verification having tight integration of verification techniques
JR Burch, V Singhal
US Patent 6,308,299, 2001
362001
Analysis of combinational cycles in sequential circuits
TR Shiple, V Singhal, RK Brayton, AL Sangiovnni-Vincentelli
1996 IEEE International Symposium on Circuits and Systems (ISCAS) 4, 592-595, 1996
351996
Trace based method for design navigation
V Singhal, JE Higgins, AN Singh
US Patent 7,137,078, 2006
322006
Design replacements for sequential circuits
V Singhal, RK Brayton
University of California, Berkeley, 1996
311996
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